A 455-Mb/s MR Preamplifier Design in a 0.8- m CMOS Process

In this paper, we present a CMOS preamplifier for use with magnetoresistive (MR) read elements in disk drives. The performance of the CMOS design is competitive with the more expensive current generation of BiCMOS MR preamplifiers. The measured gain for the preamplifier is 43 dB and the measured 3-dB bandwidth is greater than 273 MHz corresponding to a 455-Mb/s data rate. Likewise, the measured input-referred voltage noise is less than 0.57 nV/ Hz, and measured input-referred current noise is less than 10.54 pA/ Hz at an MR bias current of 10 mA. The preamplifier has been implemented in a 0.8m 5-V CMOS process and occupies a die area of 1.78 1.78 mm. In this paper, we introduce a new scheme to reduce current noise below that contributed by a single MOS device. This technique has the potential for even more impact for future submicron processes. We also showed that voltage amplifiers offer lower noise than transimpedance amplifiers for similar gain and bandwidth constraints.